This project involves the development of analytic models that can be used to evaluate the performance of computer systems. During the past year, tools for modeling and analyzing computer systems using the graph theoretic model called Timed Place-Transition (P-T) Nets were developed. This included the introduction of four special nodes, the determination of new methods for finding net invariants, and the derivation of new relationships among net variables from net structure. Using these results, a method was developed for evaluating computer system performance with Timed P-T Net models. This method was used to model and analyze the bus arbitration techniques that occur in digital systems. In addition, a state variable P-T Net model of the interconnection of two or more microprocessors was developed. This model provides a framework for determining the avoidance of deadlock and the maintenance of throughput in multiple microprocessor systems. In FY83, this work with Timed P-T Nets will be continued.